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Senior Design Verification Engineer

European Tech RecruitCounty Cork, Ireland
On-site · CorkMid-Senior Level
Posted 2h ago

Skills

  • UVM
  • FORMAL VERIFICATION
  • SYSTEMVERILOG
  • RTL
  • ASIC
  • C
  • C++
  • PYTHON
  • PERL
  • SHELL SCRIPTING
  • SYSTEMC
  • MATLAB

About the role

Senior Design Verification Engineer


European Tech Recruit are working closely with a leading semicon company, based in the county Cork area, who are looking for a talented Senior Design Verification Engineer to join their team.


Responsibilities as Senior Design Verification Engineer:

  • Apply leading-edge verification methodologies, including UVM and Formal Verification, to ensure high-quality deliverables.
  • Develop and maintain testbenches and verification components such as UVCs, C models, and reusable vertical and horizontal verification environments.
  • Verify RTL of sensor algorithms to meet ASIC tapeout quality standards.
  • Create comprehensive test plans based on design specifications and collaborate with design and systems engineers for validation.
  • Integrate C models into the UVM framework for efficient verification.
  • Write and maintain SystemVerilog assertions to enforce design correctness.
  • Perform debugging, verification, optimization, and bit-exact comparisons with provided test vectors.
  • Support the integration of designs into higher-level subsystems, including test planning, test vector generation, and debugging at the integration stage.
  • Utilize Python automation to streamline workflows and improve team productivity.
  • Document all verification activities, including test plans, results, and methodologies.


Requirements:

  • Bachelor’s degree in Science, Engineering, or a related field.
  • Minimum 3 years of experience in ASIC design verification, UVM-based functional verification, or a related role.
  • Experience with gate-level simulation debugging and power extraction tools is an advantage.
  • Strong experience building and managing constrained-random verification environments using UVM and coverage-driven verification methodologies.
  • Extensive experience using RTL simulation tools.
  • Proficiency in UVM, SystemVerilog, and shell scripting (Perl/Python).
  • Familiarity with C/C++ is a plus.
  • Debugging experience.
  • Experience with formal verification tools a bonus.
  • Familiarity with SystemC and Matlab is a bonus.


If this role is of any interest please apply directly on LinkedIn or send a copy of your CV to nh@eu-recruit.com.


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