STA Design Engineer

A Global semiconductor giant based in Cork are seeking to bolster their team with a talented STA Design Engineer.

Please note this opportunity is based on-site in Cork and requires rights to work in Ireland already in place before starting.

Responsibilities

• Perform static timing analysis (STA) and drive timing closure for complex cores and full-chip SoCs.
• Enhance and refine STA methodologies, flows, and best practices to improve accuracy and efficiency.
• Ensure adherence to timing signoff checklists, criteria, and project milestones.
• Automate timing and power data mining, analysis, and reporting to streamline workflows.
• Collaborate across design, synthesis, and physical design teams to resolve timing issues and support smooth project execution.

Requirements

• Strong expertise with STA tools such as PrimeTime, PrimeShield, or Tempus; familiarity with Tweaker, PrimeClosure, PTECO, or Tempus ECO.
• High proficiency in automation scripting using Python, Tcl, or Perl.
• Solid understanding of ASIC design flows from RTL through GDSII, with experience in large SoC environments.
• Experience with extraction and circuit simulation tools; interest in Design for Parametric Yield is a plus.
• Excellent problem-solving, communication, and teamwork skills, with 4+ years of relevant industry experience.

If this role is of interest please apply directly on LinkedIn or send a copy of your CV to alex@eu-recruit.com.

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